JPEG-C
8-bit Baseline JPEG Codec with Optional Video Rate Control
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The JPEG-C core from Alma Technologies is a standalone and high-performance, half-duplex 8-bit Baseline JPEG Codec for still image and video compression applications. Full compliance with the Baseline Sequential DCT mode of the ITU-T T.81 JPEG standard makes this IP core ideal for interoperable systems and devices. The JPEG-C is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
In addition to the standard defined Baseline JPEG streams, the core is also capable of supporting the video payload of many (de facto) standard motion JPEG container formats. The JPEG-C can also be enhanced with an optional add-on bit-rate control block, which will benefit the bandwidth constrained applications.
The core is designed with easy-to-use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed and rigorously verified, the JPEG-C is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.
IP Deliverables
Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
Self-checking testbench environment sources, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Symbol
Features
Baseline ISO/IEC 10918-1 JPEG Compliance
Programmable Huffman Tables (two DC, two AC)
Programmable Quantization Tables (up to four)
Up to four color components
Supports all possible scan configurations and all JPEG formats for input and output data
Supports any image size up to 64K x 64K
Supports DNL and restart markers
Additional Processing Capabilities
Motion JPEG payload support Rate-Control (optional)Ease of Integration
Registered I/O ports
Simple, microcontroller like, programming interface
High speed, flow controllable, streaming I/O data interfaces
Simple and FIFO like
Avalon-ST™ compliant (read latency 0)
Decoding:
Stand alone operation
Automatic self-programming by JPEG markers parsing
Marker errors catching
Broadcasting of decoded image parameters for controlling peripherals such as a block-to-raster scan converter
Encoding:
Single clock per input sample processing rate
Fully programmable through standard JPEG marker segments
Automatic JPEG markers generation on the output
Automatic program-once encode-many operation
Easy System Implementation and Verification
Extensive documentation
Bit Accurate Model (BAM)
Test Vector generation
Self checking testbench environment
Sample BAM scripts
Synthesis scripts
Simulation scripts
Place & Route scripts for FPGAs
Trouble-Free Technology Map and Implementation
Fully portable HDL source code
No internal tri-states
Scan-ready design
Strictly positive edge triggered design using D-type only Flip-Flops
Fully synchronous operation
No need for special timing constraints
No false paths
No multi-cycle paths
No special handling paths