LJPEG-D
Lossless JPEG Decoder
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The LJPEG-D IP Core from Alma Technologies is a matching decoder for the Alma Technologies Lossless JPEG Encoder and supports up to 16-bit per component Numerically Lossless decoding. Coupled with the LJPEG-E, the decoder is ideal for image and video compression applications where bit-by-bit accurate reproduction of an image is essential, while the amount of compression needed is very low and the silicon resource usage is critical. The LJPEG-D is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
The LJPEG-D is based on the spatial (sequential) lossless compression mode (SOF3) of the ISO/IEC 10918-1 JPEG standard. Rather than the Discrete Cosine Transform (DCT) functions used for lossy JPEG compression - which introduce round-off errors - Lossless JPEG employs a predictor function and compresses images by encoding the prediction error with no information loss.
The core is designed with simple, fully flow-controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the LJPEG-D is a compact, reliable and easy-to-use and integrate IP.
IP Deliverables
Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
Self-checking testbench environment sources, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Symbol
Features
ISO/IEC 10918-1 (Annex H) Compliant Lossless JPEG Decoder
Up to 64K x 64K image resolution
1, 2 or 3 (4:4:4 only) image components
2-16 bit per image component
Up to 4 stream programmable Huffman Tables
Stream programmable Restart Interval
Stream programmable Point Transform function
Limitations with Respect to the ISO/IEC 10918-1 Standard
Up to 3 image components are supported
(Nf field of the SOF3 marker segment = 1 or 2 or 3)
Single-scan
(Only one SOS marker segment, with Ns field = Nf)
The DNL marker is not supported
(Y field of the SOF3 marker segment > 0)
Fixed parameters
No sub-sampling
(Hi and Vi fields of the SOF3 marker segment = 1)
Prediction function is fixed to the left-hand predictor
(Ss field of SOS marker segment = 1)
Ease of Integration
Single clock cycle per decoded sample throughput
Simple, microcontroller like, programming interface
High-speed, flow controllable, streaming I/O data interfaces
Simple and FIFO like
Avalon-ST compliant (ready latency 0)
AXI4-Stream compliant
CPU-less, standalone operation
Trouble-Free Technology Map and Implementation
Fully portable, self-contained RTL source code
Strictly positive edge triggered design
D-type only Flip-Flops
Fully synchronous operation
No special timing constraints required
No false paths
No multi-cycle paths